Audio device and method

ABSTRACT

The present invention provides a method of operating a digital audio device, the method comprising: receiving a voice call; receiving another digital audio signal which is not a voice call; mixing the two received signals; transmitting the mixed signal wirelessly to another device.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. patent application Ser. No. 11/318,596,filed on Dec. 28, 2005, now U.S. Pat. No. 7,885,422, the entiredisclosure of which is hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to digital apparatus, methods andsignalling for enabling communications between a number ofinter-connected circuits, and is especially though not exclusivelyrelated to digital audio communications in a digital audio convergencedevice such as a Smartphone.

BACKGROUND OF THE INVENTION

A bus is a shared communications path comprising a number of conductorsconnected to a number of devices, chips or circuits for example chips onan integrated circuit board. By using a contention protocol, a sub-setof the circuits can use the bus for their own communications purposesfor a period of time. A bus therefore reduces the number of conductorsneeded to provide communications between a number of inter-connectedcircuits which is highly valued in IC and other small scaletechnologies, resulting in reduced size and cost. However the need forsharing the bus can preclude certain modes of communication and hencelimit the range of possible system functionality.

Audio convergence devices are increasingly popular, and generally allowthe execution of different types of audio applications, oftensimultaneously, on the same device. An example of an audio convergencedevice is a Smartphone, which provides both telephony-based audioapplications such as voice calls and device-centric audio applicationssuch as MP3 music playback. The Smartphone can be thought of as acombination of a mobile or cellular telephone and a PDA or palmtopcomputer. Other examples of audio convergence devices include laptopcomputers with telephony capability; or indeed any wireless telephonydevice for example a mobile phone also having device centric audioapplications such as MP3 playback.

The audio processing required of the two types of audio signals is verydifferent, for example with telephony applications such as a duplexphone call, real-time signal processing is required and the applicationis very sensitive to latency. However the fidelity of the sound or voiceaudio data is relatively low, typically a single or mono 8 kHz channel.On the other hand, whilst playing back stored music such as MP3 tracksdoes not require the same level of real-time processing ability, thequality of the audio data is often much higher, for example two orstereo channels of 44.1 or 48 kHz per channel.

These different requirements have been handled by largely separating thetwo processing chains and utilising separate processors for each task, aspecialised (communications) DSP core or chip for the telephony and ageneral purpose (applications) CPU for the device centric audioapplications. Both are complex systems in their own right, and operatewith largely different interfaces and protocols, so are designed largelyindependently, even if integrated on a common substrate. This divisionof hardware and processing is described in more detail in “ImplementingHi-Fi Cellular Convergence Devices Using Intel Xscale Technology”, ScottPaden, Dudy Sinai, WINHEC 2004.

A problem with this approach however is that because of cost, size andpower constraints, the two sides (communications and applications) ofthe device must share the audio transducer resources, for exampleexternal speaker and headphones. The above reference considers the IntelPCA chip architecture for mobile devices and analyses the pros and consof using two codecs, each dedicated to a respective processor(communications processor or applications processor), or a single codecassociated with one or other of the processors but controlled by it toprovide audio transducer services for both processors. A further optionis to use a “dual” codec which provides codec functionality for bothprocessors. An example of a dual audio codec chip or IC is the WolfsonMicroelectronics WM9713.

Whether the audio codec requirement is implemented as separate circuitsor integrated together, the separate processors need to communicate witheach other and with the codec or codecs. However this makes furtherdemands on the shared audio data bus which can further limit systemfunctionality.

SUMMARY OF THE INVENTION

In general terms in one aspect the present invention provides a busarchitecture which allows simultaneous communications sessions such asaudio data transfers between circuits interconnected by the shared bus.The bus includes a pass device or circuit which in one mode divides thebus into two or more sections such that circuits connected to one of thesections can communicate without interference from circuits connected tothe other section. The pass device in another mode allows communicationacross it such that the bus is effectively not sectioned.

In an embodiment a resistor divides a PCM bus into two sections for someapplications, such that a communications processor and an audio codeccan communicate on one section whilst simultaneously allowing anapplications processor and a wireless codec to communicate on the othersection. In another application the resistor allows communicationbetween the communications processor and the wireless codec, “across”the resistor or pass device.

By providing a digital audio bus architecture with unitary and dividedor dual modes of operation the embodiment reduces the number of busesrequired and therefore allows further miniaturisation of an audioconvergence device supporting two or more types of audio, for example“lo-fi” telephony voice and hi-fi music.

In one aspect the present invention provides a circuit for processingaudio signals and comprising: a bus having two bus sections controllablycoupled together by a pass device; a first sub-circuit coupled to afirst bus section; a second sub-circuit coupled to a second bus section;and a bridge sub-circuit coupled to both bus sections; the bus beingoperable in two modes either to allow simultaneous transmissions betweenthe bridge sub-circuit and the first and second sub-circuits using thetwo bus sections separately, or to allow transmissions between the firstand second sub-circuits using the two bus sections together.

This allows simultaneous transmissions of two audio data communicationson different bus sections, or a single transmission on both sections.This in turn allows for a greater flexibility and number of audio basedapplications for audio convergence devices.

In an embodiment, the first sub-circuit comprises a wireless codec forwirelessly communicating the audio data with a wireless peripheraldevice; the second sub-circuit comprises a communications processor forcommunicating the audio data with a phone network; and the bridgesub-circuit comprises an audio codec for decoding the audio data anddriving an audio transducer, and an applications processor for recordingand/or reading the audio data, the audio codec and applicationsprocessor coupled together independently of the bus.

This means that the wireless codec and the communications processor canprovide a phone call to the user in one mode of operation of the bus; orthe phone call can be directed to the audio codec and music providedfrom the applications processor to the wireless codec in another mode ofoperation of the bus. In the later mode the bus is effectively split bythe pass device, whereas in the former mode the bus is unitary. Variousother audio applications enabled by this dual mode capability aredescribed in detail below.

The pass device may be a passive device such as a resistor; which ischeap to implement. Alternatively it may be implemented by an activecircuit for example utilising a switchable uni-directional buffer whichprovides greater isolation between the bus sections in the split mode ofoperation and may allow for a faster data rate on the bus in the unitarymode.

For the purposes of this specification a wireless codec comprisescircuitry for interfacing with an audio data bus and with a localwireless device such as a handset via radio circuits. In other words itconverts digital audio signals in one format (e.g. PCM) on the bus intowireless signals in another format (e.g. Bluetooth™ (BT) or otherwireless technologies such as Wi-Fi—the suite of IEEE802.11 airinterface protocols including a, b, and g or Wi-MAX IEEE802.16). Forportable audio devices typically Bluetooth will be used for transmissionof audio wireless signals to a wireless headset in order to minimisepower consumption, reduce silicon real-estate or size, and reduce cost.Typically this is implemented using a Bluetooth™ chipset. Again suitableBluetooth (or other wireless) codecs will be known to those skilled inthe art, for example Texas Instruments BRF6100, BRF6150 and BRF6300.

A communications processor comprises circuitry for interfacing with theaudio bus and with an external communications network such as a mobilephone network and is typically implemented with a digital signalprocessing (DSP) core to implement functions such as managing a trafficchannel and possibly a control channel with an external network andreformatting traffic data between the audio bus data format and thatused by the traffic channel to the external network. In the describedembodiments, the external network is a wireless cellular network such asa GSM or COMA based network, however other network types could be usedfor example those defined by the WiMax IEEE802.16 or Wi-Fi IEEE802.11protocols; or a cordless phone protocol such as DECT. In someembodiments the communications processor may be implemented as a secondwireless codec.

An applications processor is typically a general purpose centralprocessing unit (CPU) configured by software to implement functions suchas store/retrieve data from local memory, convert between digitalformats and control other circuitry within an audio convergence device,typically including operation of the audio bus(es). In some embodimentsthe applications processor may include an audio bus interface such as ahardwired PCM or AC'97 interface. Typically the applications processorwill be in overall control of the audio device, for example controllingthe audio and wireless codecs and the communications processor.

An audio codec (coder-decoder) comprises circuitry for convertingdigital audio signals to analogue audio signals and vice versa forcoupling audio transducers such as speakers and microphones or legacyanalog signal sources such as gramophone turntables to digital audiocircuitry. In the described embodiments the audio codecs incorporate twoor more digital audio bus interfaces such as PCM or AC'97. Audio codecsin some embodiments also include mixers, volume/gain stages, and audio“effects” such as graphic equalisers or 3-D enhancement. Typically theaudio codec is optimised for low-power consumption, and operates off lowvoltages, e.g. 3.3V or lower.

In an embodiment a sub-circuit coupled to the first bus section and asub-circuit coupled to the second bus section each have a buffer forcoupling to the bus. Each buffer receives an input signal and hasdriving circuitry arranged to drive the bus to a voltage level dependenton the input signal. Each buffer also receives an independent enable ordisable signal which prevents the buffer driving the bus, i.e. it placesthe buffer into a high-impedance or tri-state mode. This arrangement canbe used to avoid contention on the bus when a resistor is used as thepass device.

In another aspect there is provided a digital bus circuit such as a PCMbus and comprising a bus conductor such as a single or duplex datawire(s) having two bus sections. This is suitable for the transfer ofaudio data between connected devices, but may also be used for otherapplications requiring a “split-able” bus. Each bus section is connectedto a pass circuit such as a resistor or active switchable isolatingcircuit, and also to two bus interfaces for respective circuits.Examples of the circuits include a communications processor, anapplications processor, an audio codec and a wireless codec for use in adigital audio device. At least three of the bus interfaces comprise atri-state output buffer having a tri-state, not outputting or enabledmode and one or more logic output modes (e.g. 1 and 0). The otherinterface may be receive-only for example, and so not require an outputbuffer.

In a unitary bus mode the tri-state output buffers are arranged suchthat only one of said output buffers is not in a tri-state mode, itbeing in a high voltage or a low voltage logic output mode or state forexample. In other words only one of the output buffers is“transmitting”. The high and low logic output voltages may correspond tofor example 5V and 0V respectively, or some other uni-polar voltagearrangement, or the low voltage logic mode may correspond to a negativevoltage such as −5V for example. In the unitary mode, the pass circuitis arranged to substantially couple said bus sections. In an embodimentthis is achieved by switching an active pass circuit to connect the twobus sections together. In another embodiment, this is achieved bysetting an appropriate value for a passive component or device such as aresistor or MOS device acting as a resistor. The state of the buffersmay be controlled by the applications processor for example, ordedicated bus control logic.

In a dual bus mode the tri-state output buffers are arranged such thatonly one of the output buffers connected to each bus section is not in atri-state mode and the pass circuit is arranged to substantially isolatesaid bus sections. In other words one of the output buffers connected toeach bus section is outputting a logic value or voltage which does notinterfere with the logic output on the other bus section. The passdevice may be controlled or switched so as to isolate the two bussections, for example by turning off a connecting buffer, or a passivedevice such as a resistor may be suitably sized in order to achieve thesame practical effect.

In an embodiment where the pass circuit comprises a resistive circuit,device or component, the pass device is arranged to have an impedancehigher than the output buffer impedances such that when one of saidoutput buffers on one of the bus sections is in a high voltage logicoutput mode and the another said output buffer on the other bus sectionis in a low voltage logic output mode, the voltage drop across the passcircuit is more than half the voltage difference between voltagescorresponding to the high voltage logic output mode and the low voltagelogic output mode of the respective output buffers. In other words, theimpedance of the pass device in either mode (for example a passiveresistor) can be sized or arranged such that the output impedance of theoutput buffers is less than 50% of the impedance of the pass circuit. Inan embodiment, a more stable or secure example of 2% is used, thoughvarious values above and below this could be used, for example 15% or1%.

The resistive device could simply be a resistor, however other resistivecomponents or circuits could alternatively be used, for exampleMOS-resistors or their JFET equivalents.

In an embodiment data is encoded or formatted using pulse codemodulation (PCM) for communication across the bus sections, howeverother digital data formats could alternatively be used, for exampleaudio codec '97 (AC97), or formatting for a 2/3/4 wire bus such asSerial Peripheral Interface (SPI) bus, or a Microwire™ (NationalSemiconductor) bus. The bus may be configured with simplex or duplexdata conductors, with or without clock and/or control conductors. Passcircuits may be used to separate clock and/or control bus conductorsections associated with the data bus conductors, or these may beunitary. The bus may be suitable for the transfer of digital audio data,or it may be implemented for the communication of other types of data,control signals or even clock signals. In other words it may be usedsolely to controllably divide two clock, data or control domains.

In an embodiment, the two bus interfaces coupled to a first of the bussections are coupled respectively to a communications processor forprocessing digital voice calls and to an audio codec for processingdigital audio signals into analogue audio signals, and one of the businterfaces coupled to a second of the bus sections is coupled to awireless codec for wirelessly transmitting and receiving digital audiosignals.

The other bus interface coupled to the second bus section may be coupledto an applications processor for processing digital audio signals. Theaudio codec may be coupled by a separate digital bus circuit to theapplications processor for processing digital audio signals. Theseparate digital bus may use different digital formatting than the mainshared digital audio bus, for example AC and PCM respectively.Alternatively, the other bus interface coupled to the second bus sectionmay be coupled to the audio codec; in this case the audio codec havingtwo bus interfaces (e.g. PCM), one interface connected to one bussection and the other interface section connected to the other bussection.

In another aspect there is provided a digital audio bus circuitcomprising: a bus conductor having two sections connected to a passcircuit; a first bus section being coupled to a communications processorfor processing digital voice calls and to an audio codec for processingdigital audio signals to analogue audio signals, and a second bussection being coupled to a wireless codec for wirelessly transmittingand receiving digital audio signals; wherein the digital audio bus isarranged in use to be switchable between a unitary mode in which digitalaudio signals on one of the bus sections are coupled by the pass circuitonto the other bus section, and a dual mode in which digital audiosignals from one of the bus sections are not coupled by the pass circuitonto the other bus section.

Switching between the unitary mode and the dual mode may be achievedwith control of the communications processor, the audio codec and thewireless codec, and using a passive device acting as the pass circuitand having an appropriate value in order to isolate the bus sections inone mode and couple them in the other mode. Control of the circuitsconnected to the bus sections (e.g. communications processor) comprisescontrolling their connections or interface with the bus sections, forexample to transmit or receive or to isolate.

In an alternative arrangement, an active circuit may be used toimplement the pass circuit in which case this may be suitably controlledtogether with the devices or circuits connected to the bus conductors inorder to switch between the unitary and dual bus modes. In an embodimentthe pass circuit or device is switchable between a high impedance modeand a low impedance mode.

The bus circuit may be simplex, or may comprise a second bus conductor,a second pass circuit and corresponding second couplings to thecommunications processor, audio codec, and wireless codec and arrangedto implement a duplex digital audio bus.

In general terms in another aspect, there is provided an audio codecarchitecture which is configurable or switchable into a number offunctional arrangements in order to provide audio data processingfunctions. The audio codec comprises one or more digital to analogueconverters (DAC) and/or analogue to digital converters (ADC) in order toconvert digital audio signals into analogue audio signals and viceversa. The audio codec also comprises two or more digital audio businterfaces, for example a PCM interface for coupling to the dual modebus circuit described above and an AC interface for coupling to theapplications processor described above. Alternative arrangements canalso be employed, for example two PCM interfaces connected to differentPCM bus sections. Other interface types and connections are alsocontemplated. In an embodiment the audio codec also comprises digitaland/or analogue adders, multipliers, sample rate and digital formatconverters, and a switching matrix controllable to couple a number ofthese circuit elements between the two digital audio bus interfaces.

In one aspect there is provided an audio codec for converting digitalaudio signals to analogue audio signals, the audio codec comprising twodigital audio bus interfaces for coupling to respective digital audiobuses and a digital-only signal path between the two digital audio businterfaces, such that no analogue processing of the audio signals occursin the digital-only signal path. In its simplest form, where the twodigital audio bus interfaces use the same sample rate and digitalformat, the digital audio data can be simply transferred from oneinterface to the other. Some simple manipulation and retiming of thesignal may be employed for example involving some temporary signalstorage such as a FIFO. The digital only signal path may also comprise adigital format conversion function where the two digital audio businterfaces use different digital formats, for example PCM and AC. Thismay involve repeating or omitting samples if the input and output datarates are different. Some embodiments may comprise digital signalprocessing, for example volume control, digital filtering, or mixing ofother signals, or sample-rate-conversion, involving digital addition andmultiplication of the signals.

An example of functionality of the audio codec achieved by appropriateconfiguration of the switching matrix includes adding together digitalaudio signals received from both said digital audio bus interfaces, andtransmitting the combined signal from one of said digital audio businterfaces. This may include scaling one of the received digital audiosignals compared with the other received digital audio signals beforesaid addition of the received signals. Sample rate and/or digital formatconversion may also be implemented where the digital interfaces aredifferent.

The so configured audio codec may be usefully combined with othercircuitry such as the applications processor, communications processor,and wireless codec mentioned above to perform audio processing functionssuch as combining a received call with background music.

The audio codec may additionally comprise an analogue signal path forprocessing a received digital audio signal, the analogue signal pathcomprising one or more signal analogue processing elements such asdigital-to-analogue converters, analogue-to-digital converters, adders,and multipliers. The ADC and DAC may have different sample rates inorder to implement sample rate conversion of one of the received digitalaudio signals.

The audio codec may comprise simplex or duplex digital only signalpaths, and the internal configuration or connections of the audio codecmay be different for the different signal paths. A path with analogueprocessing may be used to complement the digital only path.

In another aspect there is provided an audio codec for convertingdigital audio signals to analogue audio signals, the audio codeccomprising: two digital audio bus interfaces for coupling to respectivedigital audio buses; means for adding together digital audio signalsreceived from both said digital audio bus interfaces, and transmittingthe combined signal from one of said digital audio buses.

The audio codec may also include digital sample rate conversion (SRC) inone or both input paths. Where both input paths have sample rateconversion, one may be achieved in the analogue domain using suitableDAC and ADC conversions, and the other in the digital domain. The addingmay be implemented digitally or by converting to the analogue domain andusing an analogue adder and/or multiplier before converting back to thedigital domain.

The audio codec may form part of a larger digital audio device, whereinone of the interfaces is coupled to a communications processor forprocessing a voice call and the other interface is coupled to anapplications processor for processing digital audio signals.

In an embodiment, an AC digital audio interface is used to couple toanother circuit such as an applications processor, and this isconfigured with three or more audio channels. These channels can bemapped to two or more other digital audio interfaces, for example simplyto route digital audio signals to different circuits coupled to theaudio codec, or additionally with audio signal processing performed bythe codec. More generally the audio codec could be used to coupletogether circuits having incompatible digital audio interfaces, forexample an applications processor with an AC only interface beingcoupled to a PCM digital audio bus.

Where the audio codec comprises two PCM digital audio interfaces, thesecond such interface may simply comprise a single data pin, the othercontrol and clock pins being shared with the first PCM interface. Thisarrangement can be used to couple both sections of the above mentioneddual mode PCM bus architecture.

These audio codec arrangements may be advantageously combined with thedigital bus and audio device arrangements outlined above, however theseaudio codecs can be implemented independently of these bus and audiodevice arrangements. For example the audio codec may be used with a buswithout a pass circuit or otherwise “split-able” digital audio bus.

In general terms in another aspect the present invention providesmethods of operating a digital audio device such as a smart phone orcommunications enabled PDA in order to perform a number of audioprocessing functions. These methods may be implemented using the digitalbus, audio device and/or audio codec arrangements outlined above, orthey may be implemented using a different audio device and/or bus and/oraudio codec arrangement.

In one aspect there is provided a method of operating a digital audiodevice, the method comprising: receiving a voice call such as a GSMconnection; receiving another digital audio signal such as an MP3playback and which is not a voice call; mixing the two received signals;and simultaneously transmitting the mixed signal wirelessly to anotherdevice, for example using a Bluetooth (BT) connection.

The feature of receiving another digital audio signal which is not avoice call can include receiving this from an internal digital audiodevice component such as its local memory, and is not necessarilyrestricted to receiving the signal from an external source; althoughthis may have occurred at an earlier time for example downloading an MP3track from the Internet via the communications processor onto the localmemory.

In an embodiment this is implemented using the dual bus mode to receivevoice call signals over one bus section and transmit the mixed signal toa wireless codec over the other bus section. However other methods ofimplementing this functionality could alternatively be used, for exampleusing two separate audio buses, or a (normally) control bus such as aUART. In an embodiment the mixing is implemented in an audio codec suchas one of the audio codecs outlined above, but this could alternativelybe carried out in an applications processor for example.

In an embodiment the voice call is processed by a communicationsprocessor on or coupled to the device, and the other digital audiosignal is a hi-fi signal from an applications processor. However otherreceived signals could be used, for example a signal received from awireless codec. The sample rates and/or digital formats of the tworeceived digital audio signals can be different.

In an embodiment, the method further comprises wirelessly receivinganother signal such as the other half of a duplex voice call andtransmitting this, for example over a GSM connection.

In another aspect there is provided a method of operating a digitalaudio device, the method comprising: receiving a wireless digital audiosignal from another device, storing said signal; simultaneouslytransmitting a second wireless digital audio signal to the other device;and simultaneously transmitting a third digital audio signal in responseto receiving a voice call.

In an embodiment, this is implemented using a wireless codec to receiveand transmit the wireless signals, and an applications processor totransmit the third signal, the second signal being transmitted from theapplications processor to the wireless codec. In an embodiment, thesecond digital signal can be routed from the applications processordirectly to a digital audio bus as outlined above, or via an audio codeconto the digital audio bus as also outlined above. Alternatively,different audio bus and/or audio codec architectures could be used.

In an embodiment, the first wireless digital audio signal is a digitaldictation signal, the second digital audio signal is a hi-fi musicsignal, and the third digital signal is a predetermined outgoingmessage.

In another aspect there is provided a method of operating a digitalaudio device, the method comprising: receiving a wireless digital audiosignal from another device, storing said signal; simultaneouslytransmitting a second wireless digital audio signal to the other device;simultaneously receiving a third digital audio signal associated with avoice call, storing said signal.

In an embodiment, this is implemented using a wireless codec to receiveand transmit the wireless signals, and an applications processor toreceive the third signal, the second signal being transmitted from theapplications processor to the wireless codec. In an embodiment, thesecond digital signal can be routed from the applications processordirectly to a digital audio bus as outlined above, or via an audio codeconto the digital audio bus as also outlined above. Alternatively,different audio bus and/or audio codec architectures could be used.

In an embodiment the first wireless digital audio signal is a digitaldictation signal, the second digital audio signal is a hi-fi musicsignal, and the third digital signal is an incoming voice call message.The method may further comprise simultaneously mixing the received thirddigital audio signal with the second digital signal and transmitting themixed signal wirelessly to the other device.

In another aspect there is provided a method of operating a digitalaudio device, the method comprising: communicating a duplex voice callwith another device and simultaneously wirelessly communicating saidduplex voice call with a second other device; simultaneously andindependently recording each half of said duplex voice call.

In an embodiment the outgoing and incoming audio signals are recordedseparately by an applications processor into local memory. The signalsare received by an audio codec on a PCM interface and transferred to theapplications processor over an AC interface using two AC channels.

In an embodiment, this is implemented using a wireless codec to receiveand transmit the wireless signals, and an applications processor toreceive and forward for storing the two halves of the duplex call. In anembodiment, these digital signals can be routed from an digital audiobus as outlined above directly to the applications processor, or via anaudio codec from the digital audio bus as also outlined above.Alternatively, different audio bus and/or audio codec architecturescould be used.

In another aspect there is provided a method of operating a digitalaudio device, the method comprising: communicating a duplex voice callwith another device and simultaneously wirelessly communicating saidduplex voice call with a second other device; simultaneously mixing eachhalf of the duplex voice call and storing the mixed signal, andindependently processing the received wireless voice call. In anembodiment the independent processing is monitoring the voice call forvoice activated commands.

In an embodiment, this is implemented using a wireless codec to receiveand transmit the wireless signals, and an applications processor toreceive and independently processes the received wireless call, and toforward for storing the two halves of the duplex call, including in anembodiment mixing the two halves of the duplex call before storage. Inan embodiment, these digital signals can be routed from an digital audiobus as outlined above directly to the applications processor, or via anaudio codec from the digital audio bus as also outlined above.Alternatively, different audio bus and/or audio codec architecturescould be used.

In an embodiment the signals are received by an audio codec on a PCMinterface and transferred to the applications processor over an ACinterface using two AC channels.

These digital audio device operations or applications may beadvantageously combined with the digital bus and/or the audio codecarrangements outlined above, however this is not necessary. For examplerecording a voice call between the communications processor at theapplications processor does not require a split or dual mode bus.Similarly some or all of the audio digital processing such as mixing twosignals or converting between different sample rates and/or digitalformats may be carried in the applications processor rather than theaudio codec for example.

There are also provided devices and software or computer programscorresponding to the above outlined methods. There are also providedmethods and software or computer programs corresponding to the aboveoutlined devices or circuitry.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will now be described with respect to the followingdrawings, by way of example only and without intending to be limiting,in which:

FIG. 1 shows a known Smartphone audio bus architecture.

FIG. 2 a shows waveforms on a typical PCM bus, FIG. 2 b shows thephysical structure of an AC-link and FIG. 2 c shows data structure andtiming of the AC-link.

FIG. 3 a is another bus architecture, FIGS. 3 b and 3 c illustratesaudio applications using this architecture.

FIG. 4 a shows another bus architecture and FIG. 4 b illustratessimultaneous audio file playback and call receiving applications usingthis bus architecture.

FIG. 5 a shows a known 3-wire bus, FIG. 5 b shows a dual-mode bus, FIG.5 c shows a duplex dual-mode bus, FIG. 5 d shows a multi-bit dual-modebus, FIG. 5 e shows a dual-mode bus with pass devices in clock lines.

FIGS. 6 a and 6 b illustrate operation of the bus of FIG. 3 a in moredetail.

FIGS. 7 a, 7 b, 7 c and 7 d illustrate operation of the bus of FIG. 4 ain a second (split) mode of operation.

FIGS. 8 a, 8 b, and 8 c are circuit diagrams of active pass devices forthe bus of FIG. 4.

FIGS. 9 a, 9 b, 9 c, 9 d, 9 e, and 9 f show examples of the internalcomponents and connection paths of an audio codec.

FIG. 10 a shows a modified version of the architecture of FIG. 4 inwhich the audio codec couples to the bus on both sides of the passdevice; FIGS. 10 b and 10 c show applications using this modified busarchitecture.

FIG. 11 a shows a bus architecture similar to FIG. 4 but comprising aduplex bus; FIGS. 11 b, 11 c, 11 d, and 11 e show applications usingthis duplex bus architecture.

FIG. 12 a shows architecture where the audio codec may monitor bothdirections of data on the dual bus, and FIGS. 12 b and 12 c showapplications using this mode of operation.

FIG. 13 a shows a modified version of the architecture of FIG. 11 inwhich the audio codec couples to the bus on both sides of the passdevice; FIGS. 13 b, 13 c, 13 d, and 13 e show applications using thismodified bus architecture.

DETAILED DESCRIPTION

Referring to FIG. 1, the audio based architecture of an audioconvergence device such as a Smartphone is shown and comprises acellular radio 1 such as a GSM transceiver; a memory 2 for storing audiofiles such as MP3, MIDI, and WAV (or any program code used to run theplatform); a communications processor 3 such as a specialised DSP; anapplications processor 4 such as a general purpose CPU; a dual audiocodec 9; various audio transducers shown generally as 10 and including amicrophone, a speaker, and headphones; buses 5, 6, 7, and 8 between thecommunications and applications processors 3 and 4 and the codec 9.

The type or format of the buses (5, 6, 7, 8) or connections between thecircuits will depend on their function and the types of data to betransferred as known, and will typically include: a serial connection 5such as a UART bus between the communications and applicationsprocessors 3 and 4; a PCM or pulse coded modulation bus 6 between thecommunications processor 3 and audio codec 9; an I2S or AC data link 7between the applications processor 4 and the codec 9; and if not usingan AC data link (7) to pass control information, a serial control link 8can be used between the applications processor and the codec 9. The PCMbus 6 provides a low latency signal path between the communicationsprocessor 3 and the codec 9, which is suitable for real-time voicecalls. The AC data link 7 provides a wide bandwidth suitable for highquality digital audio signals such as hi-fi music transferred from theapplications processor 4 to the audio codec 9.

The PCM bus 6 can be a 3- or 4-wire bus, with a bit-rate clock line CLK,a frame-rate or frame-sync clock line FS, and one or two data lines DATAcarrying serial digital data in say 8- or 16-bit words, synchronised tothe bit and frame clocks, as shown in FIG. 2 a. The clocks are generatedby a chosen one of the chips connected to the bus. PCM1900 is an exampleof an existing standard for such buses. In principle, a differentclocking or bus-width might be employed, even a 8- or 16-bit parallelbus for example, though usually this would be more expensive in terms ofwires and connectors, and unnecessary for the relatively slow data ratesinvolved (typically 16 bits×8 ks/s=128 ks/s).

Other types of audio buses that might be employed include 2/3/4 wire SPIor Microwire™ buses.

The main data link between the audio codec 9 and the applicationsprocessor 4 could be any data link, for example an I2S link, or otherknown 3- or 4-wire serial or even parallel interfaces. However it willtypically be an AC '97 standard compliant “AC-link”. This standard5-wire bidirectional fixed clock-rate serial digital interface comprisesfour clock and data lines and a codec reset line as shown in FIG. 2 b.It handles multiple input and output PCM audio streams, as well ascontrol register accesses, employing a time division multiplexed (TDM)scheme that divides each audio frame into 12 outgoing and 12 incomingdata streams, each with 20-bit sample resolution, together with a TAGtime slot, as shown in FIG. 2 c. The MSBs of the TAG slot indicate whichfollowing time slots contain valid data. According to the AC '97standard, the first two time slots are concerned with reading or writingregisters on the codec, the next two are for left-channel andright-channel audio data, and the other timeslots are also assignedvarious uses for other audio and modem channels or modem control,including the possibility of increasing the effective audio sample rateby using other slots for additional samples of the left and right audiosignals.

As well as being able to carry multiple channels of audio, the AC-linkcan also make use of the TAG function to carry “Variable-Rate Audio”VRA, which means different sample rate of playback and recorded audiostreams can be simultaneously carried over the link. As an example astereo 44.1 ksps can be played back while a mono 8 ksps can be recorded.This in practice makes the AC-link a lower pin count compared with anI²S which requires as a minimum another clock (and another frame syncfor the different sample rate). AC'97 can also carry control data, whichcan avoid the need for separate control bus pins and wires.

For simplicity in explanation, the following description will refer tothe link between the audio codec and the applications processor as anAC-link, but it is to be understood that an alternative link may beused. This includes the emerging Mobile Industry Processor Interface(MIPI) Low-Speed Multilink (LML) standard. If an AC-link is not used,the additional control link 8 may be necessary, as many other links willgenerally only carry data not control information.

Also for clarity in the explanation of the architectures and signalflows, the clock lines associated with the various audio data links areomitted from the system diagrams below, as are most of the control links5 and 50 and 8.

Referring again to FIG. 1, the audio codec 9 is suitable for processingboth the real-time low bandwidth audio or voice calls and the latencytolerant but high bandwidth high quality or sample rate audio fromapplications such as stereo MP3 music playback. This “dualfunctionality” codec 9 comprises: voice optimised circuitry 9 a forprocessing voice audio data to/from the communications processor 3,including a mono DAC and ADC; Hi-Fi or music optimised circuitry 9 b forprocessing the higher sampling rate high resolution audio data to/fromthe applications processor 4, including stereo DACs and ADCs, analoguemixing and amplifier circuits; and a (analogue) link 9 c between the twocodec circuits 9 a and 9 b, typically in the analogue domain. The codec9 may or may not be integrated as a single circuit, rather than twoseparate circuits.

FIG. 3 a shows a modified system architecture including wirelessheadphone or headset capability which is an increasingly popularrequirement. Typically this is implemented using a Bluetooth™ chipset,but is termed here more generally as a wireless codec 11. Other wirelesstechnologies could alternatively be used such as Wi-Fi (the suite ofIEEE802.11 air interface protocols including a, b, and g). The wirelesscodec 11 is advantageously coupled to the PCM bus 6 between thecommunications processor 3 and the audio or local codec 9. This providesa low latency path for voice calls from the communications processor 3to the wireless codec 11. In addition wireless codecs such as Bluetoothcodecs typically already include a PCM interface so that legacyequipment or circuits can be employed. This allows sharing the sameinterface while avoiding extra pins and/or dedicated interfaces, whichrequires extra software additions and/or changes, and thus reducesdesign costs and time to market.

The applications processor 4 may transfer audio data to the wirelesscodec via a serial bus 50 such as an internal system UART or USB link ifthis is available, however typically this audio data is transferred overthe PCM bus 6 via segment 6 a. This may be achieved as shown in FIG. 3 awhere the applications processor 4 incorporates a PCM interface.

This type of audio architecture can be provided for an audio convergencedevice such as a Smartphone. As noted above a Smartphone typicallyprovides both cellular wireless communications or phone functionalityand PDA type functionality including playing audio (e.g. Hi-Fi music)files, dictating notes, voice commands and other audio basedapplications. Such devices are increasingly converged in the sense thaton-board devices are shared, such as memory which stores for exampleboth MP3 files for playback through a music player application as wellas an outgoing message (OGM) for playback to a caller interfacing withthe device's phone functions. Similarly the audio transducers are sharedin order to reduce weight, cost and size.

Referring to FIG. 3 a in more detail, the audio system architectureincludes the audio (PCM) bus 6 which inter-connects a number of circuitsincluding the communications processor 3 which handles the Smartphone'scellular wireless functionality, the wireless codec 11 which handles theSmartphone's local wireless networking functionality (e.g. Bluetooth),the applications processor 4 which handles the Smartphone's PDAfunctionality such as playing audio files from memory 2 and providingdiary and contacts functions, and the audio codec 9 which handles theprovision of analogue audio signals to the Smartphone's soundtransducers (e.g. speaker and/or headphones 10). The wireless codec 11interfaces wirelessly with a wireless headset 12 which may includeearphone speakers and/or a voice microphone.

In the mode of operation or “application” of listening to music storedin memory (possibly placed there from a disc drive), Hi-fi music signalsare typically transferred directly from the applications processor 4(having retrieved them from memory 2) to the audio codec 9 via the datalink 7 (e.g. I2S or AC97 AC-link), for playback over the device'sspeaker 10 or headphones—this is indicated by audio signal path 21 inFIG. 3 b. In Smartphones so equipped, this music may also be played backover wireless (e.g. Bluetooth) headsets 12. This requires theapplications processor 4 to transfer the music signals to the wirelesscodec 11, and this can be done by utilising the shared PCM bus 6, asillustrated by dashed line 22 in FIG. 3 b. Using the PCM bus 6 asopposed to a UART bus 50 (where this latter option is supported by boththe wireless codec 11 and applications processor 4) avoids the need forspecial profiles in both Applications processor 4 as well as thewireless codec (e.g. BT chipset) 11, which add substantially to thedesign effort, cost, and time taken to integrate the system.

In another application (see FIG. 3 c), for listening to an incomingvoice call, audio signals from the communications processor 3 (e.g. thecaller's voice) are transferred using the PCM bus 6 to the voice codec 9for playing over the speaker 10 or headphones, as illustrated by signalflow line 23. These audio signals may also be played over the Bluetoothheadsets 12 by transferring the signals to the wireless codec 11 usingthe PCM or shared audio bus 6, as illustrated by dashed line 24 in FIG.3 c.

Increasingly users of Smartphone devices wish to make use of multipleapplications or tasks simultaneously. It will be seen however that bothof the wireless headset applications described above cannot be performedsimultaneously, as the communications processor and the applicationsprocessor can not both use the shared bus 6 at the same time. Thuswhilst the user may wish to listen to an incoming voice call and at thesame time have the music still playing in the background, this is notpossible with the described bus architecture when utilising wirelessheadsets. Indeed even using the device's speaker/headphones 10 for thevoice call and the wireless headset for the audio playback is notpossible as this would still require both applications (line 23 and line22) to use the bus 6 at the same time. A possible solution to thisproblem, and more generally the problem of utilising multipleapplications simultaneously, is to incorporate additional buses into theSmartphone or similar device, however this is both expensive, and runscounter to the general aim of miniaturising the components of suchdevices.

FIG. 4 a illustrates an audio bus architecture having a further modifiedarrangement according to an embodiment and which allows simultaneous useof the audio bus by two different applications. The communicationsprocessor, wireless codec, applications processor, memory and voicecodec circuits described above are the same or similar, and are herereferenced the same as in the previous figures. This provides the same‘User Experience’ of the Local or audio codec 9 with the Wireless codec11, all whilst minimising design effort (integration) and cost(including time-to-market).

The audio (PCM) bus 36 however includes a pass device or circuit 37which in one mode of operation of the bus divides the bus into twosections 36 x and 36 y as shown. In another mode, the pass device 37 istransparent to signals on the bus 36 comprising 36 x and 36 y such thatthe bus is effectively unitary. The pass circuit 37 is located betweenthe applications processor 4 and audio codec 9 connections to the bus36, such that a first section of the bus 36 x includes connections tothe wireless codec 11 and the applications processor 4, and the othersection 36 y includes connections to the communications processor 3 andthe audio codec 9.

The pass device 37 is preferably a passive device such as a resistor.This eases implementation and cost. However active circuits or devicessuch as transistor switches may alternatively be used in order to switchbetween the two modes of bus operation as described in more detailbelow. Such switches may be controlled by the applications processor 4,and provide greater isolation between PCM signals on the two sections 36x and 36 y of the PCM bus.

The PCM bus will generally also comprise clock lines, for bit clock CLKand frame clock FS for example as shown in FIG. 2 a and FIG. 5 a. Thesecould also include pass devices as shown in FIG. 5 e, to allow separateclock domains on either side of the pass device 37 _(clk), however forthe embodiment this is not necessary. The simple dual-mode PCM bus maythus comprise three wires as shown in FIG. 5 b. The data wire includes apass device 37; however the two clock wires do not in this embodiment.Duplex or parallel dual-mode buses may comprise more data wires and passdevices, as shown in FIGS. 5 c and 5 d. For simplicity, only the datawires will be shown in most diagrams below, and a serial rather thanparallel data bus is described for simplicity; however the skilledperson will appreciate that various modifications could be madeincluding using a parallel data bus and various configurations of clockand/or control buses.

Operation of the architecture with a simple resistor as the pass circuit37 is described with respect to FIGS. 4, 6, and 7.

Operation of the bus in split bus mode can be explained by firstconsidering operation without the resistor of the bus 36, andconsidering the bus interfaces 103, 104, 109, 111 on the attached orrespective circuits 3, 4, 9, 11 respectively in more detail. FIG. 6 aillustrates a system similar to FIG. 3 a with no pass device 37, butcomprising a wireless codec 11 an applications processor 4, acommunications processor 3 and an audio codec 9. These are connected bya single wire bus 36 as shown in FIG. 6 a.

Communications processor 3 comprises a bidirectional, tri-state bufferor bus interface 103 driving the wire 36. The illustrativeimplementation shown of bidirectional tri-state buffer 103 comprisesinverter 131 which couples the logic signal on the wire 36 to thecircuitry in the main body of processor 3, to provide an input bufferhaving a high input impedance. The corresponding output buffer comprisesan inverter 132, a further inverter comprising devices PMOS 133 and NMOS134, and a series switch 135 connected to wire 36. The sources of PMOS133 and NMOS 134 are connected to a positive logic supply Vdd and anegative logic supply Vss (commonly ground) respectively. When switch135 is closed, under the control of enable signal 136, a signal D1 fromthe main body of the processor 3 is buffered by inverters 132 and133/134 and driven through closed switch 135 to produce a correspondingsignal on wire 36, at a voltage equal to Vdd or Vss for D1 high or lowrespectively. This is illustrated in FIG. 6 b. Switch 135 will usuallybe implemented as a CMOS transmission gate. The output impedance of theoutput buffer (135 and 133/134) is low, typically of the order of 100ohms when the switch 135 is closed and the output buffer is in a highvoltage (Vdd) logic mode (e.g. D1=1) or a low voltage (Vss) logic outputmode (e.g. D1=0). In a tri-state mode when the switch 135 is open, thebi-directional buffer presents a high impedance to the bus line 36.

The illustrative implementation shown of buffer 103 is not meant to berestrictive. Many other implementations of bidirectional tri-statebuffer 103 are well known. For example the function of switch 135 may beimplemented by pass transistors coupled between the supply and commondrain node of 133, 134, or by suitable logic switching the gates of 133,134.

Wireless codec 11, applications processor 4, and audio codec 9 comprisesimilar respective buffers 111, 104, 109, connected to bus 36. Similarlythese comprise respective series switches 205, 145 and 195; respectiveenable signal controls 206, 146, and 196; and respective PMOS and NMOSinverter devices 203/204, 143/144, and 193/194. In some cases, some ofthese buffers may comprise only the input or output functionality of thebuffer, i.e. be input or output buffers rather than bidirectional. Thelogic supplies Vdd and Vss are assumed to be the same or equal for allthese buffers.

Generally the buffers will be driven by suitable enable signals so thatonly one switch e.g. 135 is closed at any one time, so that only the onecorresponding interface or buffer e.g. 103 is driving wire 36 at any onetime. Configuration of the bus, involving the setting of the I/O modesof the various codecs' and processors' buffers' interfaces to the buswould normally be programmed by the applications processor, along withthe other “control” necessary to tell the other processors (and theirbuffers) what is expected from them. This can be implemented by directconnections from the applications processor to the various businterfaces, but would more typically be implemented by sending controlwords to registers in the processors, which would in turn control theenable logic lines to the individual buffers. For example this controlcommunication can be provided over UART bus 5 of FIG. 1 to thecommunications processor and UART 50 of FIG. 3 a to the wireless codec.Most of the time the buffers are enabled only when used, so no specialcommunication is required, i.e. this enabling will happen automaticallyduring the set-up of the data signal paths according to the selectedmode or application. This control including the I/O modes required forsplit mode operations of the bus would be implemented in routinesystem-level programming.

Normally the bus interfaces would be controlled so that only one of themwas driving the bus at once, i.e. all but one would be inhigh-impedance, tri-state mode. But consider the case when two switchesare closed at the same time, say 135 in 103 and 145 in 104, so twobuffers are trying to drive opposite polarity signals onto 36.

This is illustrated by the waveforms in FIG. 6 b. When both D1 and D2are low, both 103 and 104 will be trying to pull 36 low, i.e. NMOS 134and 144 will both be on, so 36 will go low, to the common negativesupply rail Vss connected to these NMOS. When both D1 and D2 are high,both 103 and 104 will be trying to pull 36 high i.e. PMOS 133 and 143will both be on, so 36 will go high, to the common positive supply railVdd connected to these PMOS. However if D1 is high and D2 low, NMOS 134will try to pull 36 down to Vss and PMOS 143 will try to pull 36 high toVdd. This has two effects. First, the voltage on 36 will end up at somevoltage between Vdd and Vss. If the NMOS and PMOS have equal drivestrength, this voltage will be half way between Vdd and Vss, but inpractice the drive strengths will be different, so one will dominate.However because of the finite output impedance of the PMOS and NMOS, thevoltage may well end up at say one-quarter of the way up from Vss toVdd, giving an uncertain logic level depending on the input logicthresholds of any logic inputs connected to 36. Second, the PMOS andNMOS of typical processors will typically be able to output tens ofmilliamps, in order to drive the capacitance of a bus with fast edges.This current will pass from Vdd through the PMOS, wire 36, and the NMOSback to Vss, giving a supply current of tens of milliamps whenever thesedevices are fighting each other. This is undesirable from a system powerdissipation perspective, especially if there are several parallel wireson the bus, and indeed continued operation in this abnormal mode maydegrade the reliability of the system.

In order to allow simultaneous transmission of data from saycommunications processor 3 to audio codec 9 and from applicationsprocessor 4 to wireless codec 11, pass device 37 is connected in thesection of wire 36 from communications processor 4 to wireless codec 11between the connections to audio codec 9 and applications processor 4,thus breaking 36 into two segments 36 y and 36 x as shown in FIG. 7 a.When both D1 and D2 are low, 103 and 104 will be trying to pull 36 y and36 x low, i.e. NMOS 134 and 144 will both be on, so 36 x and 36 y willgo low, to the common negative supply rail Vss connected to these NMOS.When both D1 and D2 are high, both 103 and 104 will be trying to pull 36x and 36 y high i.e. PMOS 133 and 143 will both be on, so 36 x and 36 ywill go high, to the common positive supply rail Vdd connected to thesePMOS. However if D1 is high and D2 low, NMOS 134 will try to pull 36 ydown to Vss and PMOS 143 will try to pull 36 x high to Vdd. Therespective waveforms are illustrated in FIG. 7 b. The voltages onsegments 36 x and 36 y will be determined by a potential divider actiondepending on the on-resistance of PMOS 143, the resistance of passdevice (resistor) 37 and the on-resistance of NMOS 134. If 37 is aresistor of say 5 kohms, and the on-resistance of each of 143 and 134are say 100 ohms each, then the voltages on 36 x and 36 y will be within2% (i.e. 100/(100+5 k+100)) of Vdd or Vss. This degradation of logicnoise margin is negligible. Also the current from Vdd to Vss will belimited to (Vdd−Vss)/5 kohm, say 660 uA for a 3.3V logic supply, whichwill be small compared to the rest of the system in any active mode.

If the resistance of 37 is increased further, the logic levels will beeven more solid, and the supply current even less. However there will beparasitic capacitances on the PCB and the logic input, and outputbuffers will present further capacitance to the bus. If the capacitanceof each segment of the bus is say 10 pf, the 5 kohm pass device willgive a time constant of 50 ns, giving delayed edges and slow rise andfall times. For a data rate of say 3 MHz (330 ns period, or 165 ns foreach half-period) this gives 3 time constants for each 165 nshalf-period, which allows the waveform to safely reach above V InputHigh level (VIH) of the target buffer for a rising edge signal, andbelow V Input Low level (VIL) of the target buffer for a falling edgesignal, so is acceptable. However higher data rates will require eitherlower resistance pass device or a reduction in the capacitances. Thiseffect is illustrated in the logic waveforms of FIG. 7 c and in moredetail by the wave shapes of FIG. 7 d. This shows the waveform on a dataline at maximum data transition frequency, with various resistance orcapacitance slowing down the edges. Waveform a is the ideal waveform,with negligible degradation of the edges. Waveform b shows acceptabledegradation. For waveform c, the waveform only just reaches VIH or VILby the end of the data pulse, so is marginally acceptable (in practicesome extra margin may be needed to guarantee adequate switchingaccording to set-up or hold times of the subsequent logic). The case ofFigure d, represents too high a pass device resistance of the loadcapacitance, with a waveform never managing to reach either VIH or VIL,giving unpredictable interpretation by the subsequent logic.

On the other hand smaller resistance values could be used for the passresistor 37, in order to increase the slew rate of the logic waveformson the bus when passing through the resistor 37. However this willincrease power dissipation and reduce the voltage swings on the twoparts of the bus. Referring to FIG. 7 a, consider the case where PMOS143 of applications processor 4 is asserting a high logic level on bussegment 36 x, to be input to inverter 201 of wireless codec 11, whilePMOS 193 and NMOS 194 of audio codec 9 are being switched to alternatelyassert high and low logic levels on bus segment 36 y, to be input toinverter 131 of communications processor 3. When both PMOS 143 and PMOS193 are on, both segments of the bus will be pulled up to Vdd, givingsolid logic signals to the two inverters. However when PMOS 193 isturned off and NMOS 194 is turned on, to try to assert a logic low levelon bus segment 36 y, the voltages on the bus segments 36 x and 36 y willbe determined by potential divider comprising the on resistance Ron 143of PMOS 143, the on-resistance Ron 145 of switch 145, the resistanceRpass of pass device 37, the on-resistance Ron 195 of switch 195, andthe on-resistance Ron 194 of NMOS 194. Ignoring Ron 145 and Ron 195 forsimplicity (or absorbing them into Ron 143, Ron 194) if say Ron 143=Ron194=Rpass/2, then bus segment 36 y will be pulled down toVss+(Vdd−Vss)/4 and bus segment 36 x will also suffer a drop in voltageto Vdd−(Vdd−Vss)/4, giving a voltage drop across 37 of (Vdd−Vss)/2. highand low. Provided the voltage level of 36 y is less than the VIL (themaximum input voltage threshold required for predictably detecting alogic low input) of 131, and the voltage level on 36 x is above VIH (theminimum input voltage threshold required for predictably detecting alogic high input) of 201, proper operation may be obtained. Howevertypically some extra voltage margin will be required to give some noisemargin to allow for extraneous noise sources. Also the above calculationneeds to be repeated for all combinations of receiving and transmittingdrivers, and for all combinations of high and low levels, and also toallow for the effects of manufacturing tolerances, particularly on theon-resistances of the MOS switches. If Rpass is decreased further, thelogic levels during contention will be further degraded, untileventually VIH or VIL is no longer safely achievable, and interpretationof the voltages by the input inverters will become unpredictable. Alsothe current from Vdd to Vss during contention is (Vdd−Vss)/(Ron143+Rpass+Ron 194), and will increase as Rpass is decreased. Foruncorrelated digital signals on the two segments, there will becontention in one direction or the other for half the time, so thiscontention current is significant. Also if the voltage levels arehovering around mid-rail, the input inverters attached to the buses willalso

The resistive pass circuit may be implemented by a simple resistorconnected to each bus section, or a MOS-based resistor in an IntegratedCircuit version for example.

Using a resistor as the pass device 37 is the simplest and cheapestsolution. However if high data rate is required, or high capacitanceinevitable, or even lower power required, an active pass device may bepreferable. FIGS. 8 a, 8 b, and 8 c show three example implementationsfor pass circuits 37 using active devices (e.g. tri-state buffers,transmission gates or transistor switches). In each case pass circuit 37will have one or more additional control terminals. These will be driventypically from the applications processor, either directly or possiblyvia some glue logic. These control terminals on devices within the passcircuit 37 are not shown explicitly in the diagrams for simplicity;however the skilled person would appreciate how control of these activedevices may be implemented.

FIG. 8 a shows a pass device 37 comprising two tri-state buffers B1 andB2 which are separately switched by signals X and Y from theapplications processor 4 for example. The associated state table showsthe different states available. Connections A and B are coupled torespective sections (36 x and 36 y) of the bus 36. When X=Y=0 both B1and B2 are in a tri-state condition so the overall pass device 37effectively divides the two bus sections 36 x and 36 y apart so thatthey operate separately such that signals on each bus section areisolated from each other. If X is high and Y low, one of the tri-statebuffers B1 is “on”, whereby a conduction path is provided from one bussection 36 x to the other section 36 y, effectively unifying the bussections 36 x and 36 y into a single bus 36. Similarly if Y is high andX low, one of the tri-state buffers B2 is “on”, whereby a conductionpath is provided from one bus section 36 y to the other section 36 x,effectively unifying the bus sections 36 x and 36 y into a single bus36. Such an arrangement only allows signals to travel in one directionat a time, i.e. the arrangement assumes a non-duplex signal path, whichis the case for a PCM bus which has a separate bus for each direction ofsignal traffic. Note X and Y both being high is not allowed, since thepair of cross-coupled buffers would then lock up into state A=B=1 orA=B=0. The tri-state buffers B1 and B2 would be similar to the buffersalready described with respect to element 103, but being unidirectionalthey would not require the inverter 131.

FIG. 8 b shows an implementation of pass device 37 as a transmissiongate with an NMOS and PMOS driven by control signal X and its inverse.If X is low, the two segments 36 x and 36 y are isolated. If X is highthe two segments are connected.

FIG. 8 c shows an alternative arrangement utilising a resistor andswitched tri-state buffer. This acts in a similar manner to the singleresistor implementation described above, but additionally includes thetri-state buffer to boost the conductivity in one direction, for exampleif 36 y presents too much capacitance to be driven through the resistor(of high value limited by desired power dissipation) but 36 x presentslow enough capacitance to be driven acceptably fast from 36 y throughthe resistor.

Thus utilising a pass circuit 37, it will be appreciated that separatecommunications can be carried out simultaneously between thecommunications processor 3 and the audio codec 9, as well as between thewireless codec 11 and the applications processor 4. This is because whenboth sections 36 x and 36 y of the shared audio bus 36 are being used atthe same time, the pass circuit 37 acts to isolate the two bus sections,substantially suppressing any current that might pass between the twosections, at least to the extent that the bus interfaces (103, 104, 109,111) of the various circuits (3, 4, 9, 11) can “filter” this out.However in other modes of system operation the pass circuit 37 appearstransparent to signals on the bus such that data can be transferredbetween the communications processor 4, “over” or “through” the passdevice 37, to the wireless codec 11 for example, provided that theapplications processor 4 output 104 sharing the second segment of thebus is tri-stated to avoid it overriding the signal passed through thepass device.

Therefore by using a passive or suitably controlled active pass circuit37, together with appropriate control of the bus interfaces, the bus canoperate in a unitary or dual mode. This in turn allows for differentapplications or functions to share the audio bus adding to possiblefunctionality of the audio convergence device or at least efficientimplementation of this functionality using this type of audio busarchitecture. In other words, this “dual mode” ability of the audio bus36 provides for additional modes of system operation, and without majormodifications to any of the components. Thus it allows for improvedfunctionality within the device, without the need for additionalhardware such as an additional audio bus and modified chips implementingthe described circuits. (Minor modifications to some existing standardaudio codecs might be required to allow some additional signal paths andhence additional functionality as outlined further below, but theprocessors and Wireless codec would not require changes.) Furthermorethere is no need for additional driver software in order to implementthis architecture as the interfaces or bus protocols (e.g. PCM) used areunchanged. Furthermore control of the bus interfaces to implement thedual or unitary mode of the bus is inherent in the use of theapplications using the bus. The only additional software that isrequired is related to the applications themselves, as opposed toutilising the dual mode audio bus arrangement. This reduces theintegration complexity associated with implementing this additionalfunctionality.

Referring again to FIG. 4 a, the communications processor circuit 3interfaces with radio circuits (1 in FIG. 1) which communicate withcellular (e.g. GSM, GPRS, 3G) base stations in order to providetelephony functionality for the device. Various circuits 3 of this typewill be known to those skilled in the art, but an example includes theIntel PXA800x GSM/GPRS communications processor. The communicationsprocessor 3 includes an audio signal interface for connecting to theaudio signals bus 36. This bus 36 is typically implemented as a PCM busin order to ensure maximum interoperability with legacy chipsets andminimise latency, but may utilise any suitable protocol as is known.

The wireless codec circuit 11 provides an interface (Over The Air) toother wireless devices local to the Smartphone (e.g. headsets 12 andlaptop computer and other remote devices), and also incorporates anaudio signals interface (e.g. PCM) or connection in order tointerconnect with an audio signals bus 36. The wireless codec 11 usesradio circuits (not shown) which wirelessly interconnect with otherdevices such as wireless headsets, as is known. Various air interfacetechnologies can be used including Bluetooth and Wi-Fi (IEEE802.11) (orWi-MAX IEEE802.16), however typically Bluetooth will be used fortransmission of audio wireless signals to a wireless headset in order tominimise power consumption, reduce silicon real-estate or size, andreduce cost). Again suitable Bluetooth (or other wireless) codecs willbe known to those skilled in the art, for example Texas InstrumentsBRF6100, BRF6150 and BRF6300 (latest generation).

The applications processor 4 is typically a general purpose processorchip which provides various PDA type functions such as calendar andcontact applications, as well as the playback of music or other audiofiles. The applications processor will also typically control theSmartphone device's screen including recognising input from the user,and the audio output in the sense of implementing the user's commands bycontrolling the configuration of itself and other devices. The processor4 is coupled to device memory 2 which stores the calendar and contactsdata as well as music (e.g. MP3) and video (MPEG4) files. In additionthis circuit 4 has a connection or (PCM) interface with the audio bus36. An example of an applications processor circuit 4 with a PCMinterface is Intel's PXA27x applications processor. More general-purposeprocessors, without PCM interfaces, may be used in some embodimentsdisclosed below.

The functions required of the audio codec 9 will vary according to therange of applications required of the system. It may contain a PCMinterface for communication via the PCM bus, a DAC for conversion ofdigital audio signals into analogue audio signals suitable for playingover the device's loudspeaker/headphones 10, and an ADC for convertingsignals from microphones. It may comprise a separate interface to a datalink such as an I²S or Intel AC (e.g. AC '97) for communicating with theapplications processor. Also it may contain various digital or analoguemixers and programmable gain stages or multipliers for mixing togethervarious signals as desired. The codec may also provide some digital oranalogue filtering or other conditioning of the audio signals.

Depending on the application or mode and on the signal source, dataarriving at or sent from the audio codec may be at various sample ratesand word-lengths. The digital audio data received from the applicationsprocessor 4 will typically be much higher quality (e.g. Hi-Fi) comparedwith that from the communications processor 3, the latter typically onlybeing a mono 8 kbs of 13 bit words channel for Voice applications (or upto a mono 16 kbs of 14 bit words for Wide-Band Voice), whereas theformer will typically be two or stereo 44.1/22.05/11.025 ksps of 16 bitwords per channel for Audio applications. In general the codec 9 willneed the capability of digital-analog conversion and analog-digitalconversion at various bit-widths and sampling frequencies, with mono orstereo operation. This may be by dedicated converters of variousperformance, connected in the appropriate signal paths. However areduced number of ADCs and DACs will suffice, connected into varioussignal paths as required, and either configurable to operate at lowerresolution, or just allowed to convert at higher resolution or samplerate with appropriate digital processing to compensate if necessary. Byusing a reduced number of converters, silicon area will be saved.

In general, in addition to the basic functions of DACs and ADCs forinterfacing digital data and the external input and output transducersor other analog signal sources or sinks, the requirements of the audiocodec include routing signals to and from its PCM and AC-link interfacesin a configurable fashion, and possibly mixing and scaling such signalsor sample-rate converting, in analogue or digital domains.

By way of example, FIG. 9 a shows components and connections within anaudio codec according to an embodiment. It comprises a DAC 13connectable to convert data (e.g. phone voice) received via a PCMinterface 40, and a DAC 14 connectable to convert data (e.g. musichi-fi) received via an I2S or AC'97 interface 41. The DAC outputanalogue audio signals are mixed by an analogue mixer 15, and can beoutput via connection 47 to a speaker, either directly or via an on-chipor off-chip power amplifier. Alternatively or additionally the DACoutput analogue audio signals may be mixed by an analogue mixer 15 a andfed to an analogue to digital converter (ADC) 16. The digitised mixedaudio signal (e.g. music playback and phone voice) can then betransmitted via over the AC or I2S interface 41, for example back to theapplications processor which may then route this mixed signal to thewireless codec so a user can listen to a voice call from the PCMinterface with background music from the incoming AC interface asillustrated in FIG. 4 b. The audio signal path within the audio codec isshown in bold in FIG. 9 a.

The audio codec will generally contain several ADCs and DACs and otherpossible signal paths. For instance the ADC output may be output on thePCM bus via link 49, for use by e.g. the communications processor for anoutgoing call. Also shown is analogue input 42, representing an inputfrom say an FM radio or other analogue signal source or transducer,which is provided as another input to the analogue mixers 15 and 15 a.

The codec 9 may also comprise digital adders and multipliers, and aswitching matrix to switch the various on-board components intodifferent configurations in order to implement different audiofunctions. Thus a digital only signal path such as 45 and 49 shown couldbe implemented between the two digital audio bus interfaces 40 and 41.This digital only signal path does not include DAC's and ADC's, norother analogue processing elements or components. This avoids anydegradation of the audio signal (e.g. additional thermal noise,distortion, crosstalk from other ambient signals) due to the conversionfrom analog to digital and back again to digital. It also allows theDAC, mixer, and ADC to be powered down, to save power. (The digital pathwill be much lower power than the analog path it replaces).

In its simplest form, where the two digital audio bus interfaces use thesame sample rate and digital format, the digital audio data is simplytransferred from one interface to the other. In practice some simplemanipulation or retiming of the signal may be necessary, involving sometemporary signal storage such as a FIFO. The digital only signal pathmay also comprise a digital format conversion function where the twodigital audio bus interfaces use different digital formats, for examplePCM and AC. This may involve simple operations such as repeating oromitting samples if the input and output data rates are different, orbit-stuffing, or reversing the bit order, or even serial-to parallelconversion, well known to those in the field.

Some embodiments may comprise digital signal processing, for examplevolume control, digital filtering, or mixing of other signals, orsample-rate-conversion, involving digital addition and multiplication ofthe signals. This may be implemented using a standard or customised ALU,or it may be by dedicated, hard-wired logic, using techniques well-knownin the field.

This simple manipulation or digital signal processing of the signal inthe digital only signal path can be performed either by suitablefunctional or circuitry blocks interposed in paths 45 or 49, or blocksin the other signal paths, as discussed below with reference to FIGS. 9c to 9 f.

The audio signals can also be adjusted at various points in these signalflows by programmable gain elements 43, 43 a, 44, 44 a, and 46, insertedas shown in FIG. 9 b.

The motivation for converting from digital to analogue and back to audioagain, despite the extra power and risk of signal degradation involved,is to cope with different data rates required in different parts of thesystem. By converting the input digital sampled data to a “smooth”continuous-time analogue waveform, and then reconverting to a new samplerate the input and output data rates can be decoupled as is known.Suitable smoothing filtering can be added easily to the DAC amplifierand mixer functions to make the analogue waveform suitably “smooth”.

If the data rates are the same, and if the mixing function is notrequired in some signal paths, these conversions can be bypassed, forexample via digital only paths 45 as shown, and the digital data routedfrom one digital audio interface 40 to the other 41. As noted above,this will require with some reformatting and retiming to convert theinput according to the outgoing bus protocol (AC) and timing fortransmission where this is different from the incoming bus protocol(PCM).

To implement scaling and mixing functions, digital audio signalsreceived from the PCM bus interface 40 (e.g. voice call) and from the ACbus interface 41 (e.g. MP3 music stream) may be multiplied and added inthe digital domain, as illustrated in FIG. 9 c. The analogue mixer 15 ais replaced by a digital adder 15 b and the analogue amplifiers 43 a and44 a are replaced by digital multipliers 43 b and 44 b, the DACs and theADC being removed from the now digital only signal path.

Even if the digital sample-rates are different, there exist knowndigital techniques for the required “Sample Rate Conversion” (SRC),generally involving conversion to a very high sample rate, low-bit-widthrepresentation, using techniques such as delta-sigma modulation or noiseshaping for example, and then converting back down using appropriateanti-aliasing filtering, to the required lower sample-rate,higher-resolution format, required as output. Alternatively, for lowercost but lower audio quality, such blocks may just omit or add in extrasamples to try and match the bit-rates. These optional blocks are showndashed as additional SRC elements 48 a and 48 b in FIG. 9 d. One or bothof these blocks may be implemented in hardware, or only one SRC may beand which is switched to a chosen input as desired, to reduce cost.Alternatively, all the digital signal manipulation or processing,including SRC, may be undertaken by a common ALU, with signals routed toit as appropriate.

However these techniques tend to be very complex and involve significantdigital signal processing. Given the codec already contains DACs andADCs for other purposes, such as driving speakers via port 47 as shown,the mixed analog-digital solution provides the advantage that it doesnot impose significant extra cost or complexity.

Further internal routing possibilities exist. For example FIG. 9 c showsin bold a digital only signal path through the configurable codec 9having a digital adder 15 b for mixing digital audio signals receivedfrom the two digital audio buses 40 and 41. Digital multipliers orscalers 43 b and 44 b may be used to adjust the magnitude of one signal(for example to reduce background music volume) compared with the other(for example increase the voice call volume).

In some applications, the input sample rates presented at interfaces 40and 41 may be different from each other, or from the required outputsample rate of the output from interface 41. For example the inputsignal at 41 could be a high-quality signal derived from an mp3 file inmemory, or a lower-quality recorded message received from memory, butstill at a different sample rate from the PCM signal from thecommunications processor. The output from 41 could be required to be ofhigh quality, when listening to the mp3 file, or low-quality, if thisoutput is merely to be recorded, possibly in a further compressedformat, in memory. FIG. 9 d illustrates a similar configuration to FIG.9 c but including a sample rate conversion function 48 a and/or 48 b inone or both of the incoming (pre-mixing) received signals. This allowsreceived digital audio signals at different sample rates to be mixed. Afurther possibility, not shown in FIG. 9 d would be for a SRC block tobe inserted between mixer 15 b and interface 41, for the case when bothinput signals are the same sample rate, but the output sample rate isrequired to be different.

FIG. 9 e shows DAC 13 and ADC 16 connected in series tosample-rate-convert a signal from the PCM interface, which is thenpresented to adder 15 b to mix this signal with one from the AC-linkinterface, possibly after digital sample-rate-conversion by 48 b, andtransmit the resulting data back over the AC-link (or over the PCM linkvia path 49 a). Thus one received signal is sample rate converted usingthe analogue domain, and re-converted to digital before digital mixingwith the other received signal. This avoids any degradation of the(possibly high-quality, mp3) audio signal received by 41 due toconversion from digital to analog and back to digital, and theunnecessary power consumption by these conversion, while allowing thepossibly lower quality signal input to 40 to be upsampled to a highersample rate before the digital mixing. This may be because the codecembodiment does not include digital SRC hardware, or if the on-chip ALU,if any, is already fully occupied performing other tasks. The otherreceived signal (shown from the AC interface 41) may or may not besample rate converted in the digital domain depending on implementationand design criteria or goals. This SRC function may use up a soleavailable hardware SRC, or may use up all the capacity of the on-chipALU, thus requiring the sample rate conversion of the signal from 40 tobe performed using DAC 13 and ADC 16 as above. The signal processingpath is shown in bold.

Similarly, FIG. 9 f shows DAC 14 and ADC connected in series tosample-rate-convert a signal from the AC-link, which is then presentedto adder 15 b to mix this signal with one from the PCM interface,possibly after digital sample-rate-conversion by 48 a and transmit theresulting data back over the AC-link (or over the PCM link via path 49a). This arrangement avoids any unnecessary digital-analog-digitalconversion, especially of higher-quality signals, while avoiding theneed to add extra SRC blocks or a more powerful ALU to the embodiment,to provide a cost-effective solution. The signal processing path isshown in bold.

Various suitable codecs will be known, but an example is WolfsonMicroelectronics' WM9713 Dual Codec (AC97 Audio+PCM Voice).Alternatively two separate codecs could be used; one for the PCM basedvoice call signals and one for the hi-fi audio from the applicationsprocessor.

It can be seen that these various internal configurations of the audiocodec give a wide range of possible combinations of signal routing,analogue or digital sample-rate conversion, ADC or DAC functions. Theoperational mode of a system using such an audio codec as the hubthrough which most audio signals pass can thus be programmed largely bythe configuration of the audio codec, rather than requiring extrasoftware or hardware associated with components elsewhere in the system.

Referring briefly to FIG. 10 a, a codec 9 is shown with three digitalaudio interfaces, an extra PCM interface 39 a having been added tocouple to the upper bus section 36 x. This obviates the need for a PCMinterface on the applications processor 4. This embodiment is describedin more detail below.

Whilst the codec 9 has been described as configurable using a switchingmatrix, fixed architecture codecs having one of the above describedarrangements could alternatively be used, for example for dedicatedfunctions.

A method of operating a digital audio device is described with referenceto FIG. 4 b, in which an application or function is enabled by thestructure of FIG. 4 a. This figure shows how to achieve the applicationof simultaneous audio playback and voice call reception, in which bothaudio files stored in memory 2 and a voice call are played to the useron wireless headsets 12. This is achieved in this embodiment byeffectively splitting the audio bus into two sections 36 x and 36 y withseparate communications on the bus between the communications processor3 and the audio codec 9, and the applications processor 4 and thewireless codec 11 respectively. A voice call is received by the digitalaudio device, and in this embodiment voice data from a GSM call forexample is transferred from the communications processor 3 to the voicecodec 9 over the lower PCM bus section 36 y, as indicated by solid line23. Additionally another digital audio signal which is not a voice callis received by the device, for example Hi-Fi music or an Audio Alert,and this audio data is transferred from the applications processor 4 tothe voice codec 9 over its AC data bus or link 7, as indicated by solidline 20. (In this context, for simplicity, “received” audio data istaken to include the cases where the data is input to the digital audiodevice some time previously, for example as an mp3 file downloaded overthe cellular radio link, or via say a USB connection, or as a messagerecorded from the Bluetooth headset, or even where a message is storedin a read-only memory or is otherwise defined during manufacture andassembly of the digital audio device.)

The two received signals are then mixed. In the embodiment the audiocodec 9 receives the audio data via its PCM and AC-link interfaces, andmixes these, with appropriate analog or digital gain control and mixing,and sample-rate conversion in analogue or digital domains, as describedabove, to produce output digital audio data or a mixed signal which istransmitted over the AC '97 interface and link 7 to the applicationsprocessor 4. The applications processor 4 then transfers this data tothe wireless codec 11 over the upper PCM bus section 36 x, as indicatedby line 25; and the mixed digital audio data or signal is thentransmitted wirelessly to another device such as the headset 12.

Thus although audio data is being simultaneously carried over bussections 36 x and 36 y, the pass device 37 ensures that these arecarried separately. If the music file finishes, or the user wants tostop listening to it, then the communications processor 3 may resumetransfer of voice data directly to the wireless codec using both bussections 36 x and 36 y with the applications processor outputtri-stated.

The dual mode audio bus allows re-use of existing single PCM interfacewireless codecs when mixing communications side (e.g. GSM voice calls)and applications side (e.g. MP3 playback) audio data streams. Thisallows lower power consumption, reduced CPU overhead, less new softwaredevelopment. Indeed no software development is required on thecommunications side, and new software is introduced only for newfeatures on the applications side, with minimum effort as it onlycontrols the codec and is not doing any additional audio signalprocessing. Furthermore there are reduced hardware costs compared withsay a more expensive dual PCM interface wireless codec and dual PCM orother bus.

In the embodiment of FIG. 4 b the audio codec 9 re-digitises the mixedanalogue signal at the wireless codec's sampling rate which is typically8 kHz. This data is then transferred from the applications processor'sPCM interface to the wireless codec 11. This can be achieved using adirect memory access (DMA) rather than using generic software code, inorder to minimise loading of the applications processor 4. The DMAroutine seamlessly transfers incoming data from the applicationsprocessor's AC-Link FIFO buffer (coupled to the AC data link 7) to theFIFO buffer for outgoing data at the PCM interface. Since theapplications processor must already be active for applications sideplayback (e.g. MP3), this simple task does not noticeably affect itspower consumption.

Whilst in the embodiment the application of mixing a voice call and anon-voice call and transmitting the mixed digital audio signalwirelessly has used the split bus architecture of FIG. 4 a, otherdigital audio device architectures could alternatively be used. Forexample two separate buses could be used, or an additional codecemployed. The embodiment however achieves this functionality withreduced power consumption, complexity and modifications to existingparts.

In an alternative embodiment illustrated in FIG. 10 a, the audio codec 9may be arranged to connect to the PCM bus 36 both above (x) and below(y) the pass device(s) 37 in order to provide its output signal directlyto the wireless codec 11 rather than via the applications processor.This requires added complexity from the audio codec 9, but simplifiesthe applications processor 4 requirements, for example by removing theneed for a PCM interface. The second PCM output of the audio codec canbe implemented by routing the ADC digitized word into the PCM interfaceas per track 49 in FIG. 9 a or 9 b and transmitting this data viaanother pin on the audio codec, which is then connected to the uppersection of the PCM bus 36 x. Usually no extra clock pins will berequired, since the clock lines in the top and bottom segments of thebus will not be isolated by pass devices, so just an extra data pinrather than a complete extra PCM interface is required in audio codec 9.However it would be possible if desired also to have pass devices in theclock lines to allow separate clock domains, at the expense of extracircuitry and pins needed to generate and output the second set ofclocks.

Examples of applications enabled by the structure of FIG. 10 a are nowdescribed with reference to FIGS. 10 b and 10 c.

FIG. 10 b shows a method of operating a digital audio device in order tomix and wirelessly transmit two received digital audio signals, and issimilar to FIG. 4 b, where background music from memory is mixed in witha received voice call. However the triple digital audio interface audiocodec 9 of FIG. 10 a is used, which obviates the need for a PCM or otheraudio bus interface on the applications processor 4. The signal flowsare similar, except that data travels from audio codec via path 25 adirectly onto the upper PCM bus 36 x, in place of through theapplications processor via path 25 of FIG. 4 b.

Where an input to the Applications processor chip from the PCM bus isneeded, this audio is received by the audio codec 9 and forwarded to theapplications processor 4 via the I2S or AC interface 7. The digital onlysignal paths described above with respect to FIG. 9 can be used toefficiently transfer the digital audio data or signals between thedigital audio bus interfaces.

FIG. 10 c shows a “Voice Dictation” application or method of operating adigital audio device where a received wireless digital audio signal fromanother device is routed via the audio codec 9 to the applicationsprocessor. In the embodiment an incoming digitised voice from thewireless codec is transferred to memory, possibly after some compression(for ‘Voice Dictation’ applications for example). The signal path 26flows from the wireless codec via the PCM bus and the audio codec'ssecond PCM data pin into the audio codec, where it is routed (andretimed and reformatted as required) for transmission on the AC '97 busto the applications processor. Thence it is written to memory (possiblyafter some data compression algorithm within the application processor).

The above embodiments have only been described with respect to one datawire in the PCM bus, and hence signals only propagating in one directionat any one time on each segment of the bus. Usually however a PCM buswill comprise two data wires, allowing data propagation in bothdirections simultaneously, i.e. duplex operation, as in FIG. 2 b.

FIG. 11 a illustrates the structure of a practical duplex bus 36, havingtwo pathways 36 a comprising 36 ay and 36 ax and 36 b comprising 36 bxand 36 by and respective pass devices 37 a and 37 b, as also shown inFIG. 5 c.

Methods of operating a digital audio device or digital audioapplications enabled by the structure of FIG. 11 a are now describedwith reference to FIGS. 11 b, 11 c, and 11 d.

One application enabled by the duplex bus is duplex voice calls, usingthe wireless headset to receive an incoming call while continuing tolisten to background music, in a similar fashion to the application ofFIG. 4 b, but with the capability of simultaneously sending outgoingaudio messages using the headset microphone. Referring to FIG. 11 b, itcan be seen that the user's voice is transmitted directly from thewireless codec 11 to the communications processor 3 over both sectionsof the second bus 36 bx and 36 by (and the pass device 37 b) via thepath 32 illustrated by the dashed line. However, in a similar fashion toFIG. 4 b, the caller's voice is transmitted from the communicationsprocessor 3 first to the audio codec 9 via path 23 over the lowersection (y) of the first bus 36 ay, where it is mixed with audio frommemory 2 via path 20 before being transmitted from the applicationsprocessor 4 to the wireless codec 11 via path 25 over the upper (x)section of the first bus 36 ax. Thus the first pass device 37 aeffectively separates the bus sections 36 ax and 36 ay of the first bus36 a, but the second pass device 37 b effectively combines the bussections 36 bx and 36 by of the second bus 36 b. The local codec 9 mustof course be controlled to tri-state its output onto 36 by to allow thewireless codec microphone signal to pass through 37 b over to thecommunications processor 3.

FIG. 11 c illustrates another method of operating a digital audio devicein which a received wireless digital audio signal such as digitaldictation is stored on the device, another digital audio signal such asMP3 music is wirelessly transmitted, and a third digital audio signalsuch as an outgoing message is transmitted in response to a voice call.This embodiment uses the architecture of FIG. 11 a, in which the user ofthe device (e.g. Smartphone) is using a digital dictation (DD)application in which audio data from the wireless headset 12 is recordedin memory 2, while music (e.g. from MP3 files) or other audio data isplayed back over the wireless headset. The system is configured suchthat the device may also respond to an incoming call from thecommunications processor 3 by playing a previously recorded automatedanswer-phone or voice-mail type outgoing message (OGM) from memory 2.

The user's voice is transferred from the wireless codec 11 to theapplications processor 4 and memory 2 for recording via path 26 a, andadditionally audio data is transferred via path 26 b from the memory 2and applications processor 4 to the wireless codec 11 for playing to theuser. These transfers 26 a and 26 b take place over the upper sections36 ax and 36 bx of the audio buses 36 a and 36 b. The outgoing message(OGM) stored in memory 2 is transferred to the audio codec 9 by theapplications processor 4 (line 27 a). If sample-rate conversion isrequired, the path through the audio codec 9 may include passing througha DAC 14 and ADC 16 or a digital SRC 48 b as discussed above. Otherwisethe data may be transferred in the digital domain from AC-link interfaceto the PCM interface across an internal path such as 45. The OGM,suitably re-digitised if necessary, is then transferred from the codec 9to the communications processor 3 over the PCM bus 36 by, (path 27 b)for playing to the caller.

Far end voice signals (shown as dashed line 28) from the communicationsprocessor 3 (e.g. talking or background noise at the caller end) areignored.

FIG. 11 d shows a similar application, but in this case the thirddigital audio signal is a received or incoming voice call message and isstored or recorded in memory, without disturbing the user, who isdictating and listening to music. The incoming message passes throughthe audio codec either directly (via the dotted by-pass path 45) or viaa DAC/ADC or digital sample-rate conversion.

FIG. 11 e shows a further “call screening” type application in whichmusic or other audio files (the second digital audio signal) are playedback to a user of the device over wireless headsets, and this is mixedwith the third digital audio signal such as an incoming message (ICM)from a caller so that the user can decide whether to answer the call orjust record the incoming message. An incoming message or voice data issent from the communications processor 3 to the audio codec 9 over thePCM bus 36 ay (lower section) (solid line 29). This message (ICM) may bein response to the OGM from the application of FIG. 6 for example. Theaudio codec passes this signal across the AC-link to the applicationsprocessor, which stores the incoming message (ICM) in memory 2, possiblyafter compressing this data.

The application processor also retrieves audio data (e.g. MP3 musicfiles) from the memory 2 via path 20, and converts this data to suitabledigital audio signals, which are then transferred to the wireless codec11 via path 25 over the PCM bus 36 ax (upper section). The applicationprocessor may also digitally mix in the incoming message, so that thesignal on path 25 is a mix of both the music and the incoming message.The combined signal is then played to the user over the wirelessheadsets 12, so that the user can decide whether to answer the call ornot, or just to record it, or to ignore it altogether.

The sample-rate of the data from the communications processor 3 willgenerally be different and lower than that of the hi-fi audio dataretrieved from the memory 2. If the incoming message is only to berecorded, then the audio codec can send this data at the original lowdata rate across the AC-link, to be processed at this low data rate bythe applications processor. This avoids consuming power in the audiocodec due to analog or digital sample-rate conversion, and also reducesthe computing bandwidth required of the applications processor 4 in itscompression, or vocoder, operations. If the signals are to be mixedhowever, either the sample-rate conversion up to the hi-fi sample rateneeds to be activated in the audio codec, or some relatively crude (butpossibly adequate for communications-quality audio) sample-rateconversion, (e.g. just repeating samples until updated) will benecessary in the applications processor, requiring extra software andpower consumption in the applications processor 4.

The communications processor 3 can be arranged to ignore an outgoingsignal (i.e. mute near-end) from the wireless codec 11 (indicated bydashed line 32) in order to prevent any near-end voice (from thewireless headset 12 microphone for example) from being heard at the farend (ie on the voice call). The communications processor can then bearranged to accept these voice signals (32) in order for the user toanswer and intercept the call (i.e. un-mute), which may be carried onwith or without the audio file from memory still being played backdepending on configuration of the device or the user's preferences.

It will be apparent that numerous other applications could also benefitfrom the dual mode nature of the audio bus 36, so that audio data frommany other applications (e.g. Karaoke, with the microphone used by thirdparties) could be transferred simultaneously over the audio data bus,for example to play mixed audio data from different applications to auser; especially over a wireless connection. Another example is an FMreceiver or other external audio source furnishing analogue signals tothe local codec 9 which are then digitized to be transferred to thewireless codec 11 with or without other voice/audio signals.

It will also be apparent that these digital audio applications ormethods of operating digital audio devices may be implemented usingother architectures, for example separate digital audio and/or controlbuses and/or additional codecs. These digital audio applications aretherefore not limited to the split mode audio bus architecture describedabove, but could be implemented on different digital audio devices.

FIG. 12 a shows a duplex PCM bus configuration. The PCM bus inputs ofthe audio codec are both set to receive signals on the duplex bus wires.There is no direct connection from the applications processor 4 to thePCM bus 36 a and 36 b. No pass elements (e.g. 37, 37 a, 37 b fromprevious figures) are shown, and this can be implemented by operatingthe bus in unitary mode, or using a standard bus without pass elements.

In some applications it is advantageous for the applications processor 4to process the two (incoming and outgoing) audio signals separately. TheAC97 AC-link interface operates with tagged time slots, including onenormally assigned to output data from the Left channel or the (stereo)ADC and one to the right channel, as described earlier with reference toFIG. 2 b. So the incoming signals can be routed digitally so for examplethe near-end signal is communicated on the left ADC slot and the far-endsignal is routed on the right ADC slot. This further extends the audioapplications that may be implemented using the shared PCM audio busarchitectures described—further examples are given below.

FIG. 12 b illustrates a method of operating a digital audio device tocommunicate a duplex voice call with another device (caller) and with awireless other device, and to simultaneously independently record eachhalf of the duplex call. The audio codec 9 simultaneously delivers tothe applications processor 4 both near-end audio (e.g. voice from theuser headset 12 to the communications processor 3 over PCM interface 36b) and far-end audio (e.g. voice from the caller/communicationsprocessor 3 to the wireless codec 11 and user headset 12 over the PCMinterface 36 a) signals. The near end signal path is referenced 51 andthe far end signal path is referenced 52.

By supplying both voice streams (near and far end or transmitting andreceiving) of a voice call to the applications processor 4, new audioapplications or functionality are enabled. For example, this allows avoice call (both caller and user voices) to be recorded into memory 2 bythe applications processor. This can be achieved without having toimplement mixing of the two channels by the communications processor 3and transfer of this mixed signal to the applications processor 4 over aserial interface (e.g. UART 5 of FIG. 1). This in turn means that nospecial communications processor drivers are needed to implement thisfunctionality, and that the quality of the voice signals is maintained.Further there is a much reduced processing load on the communicationprocessor 3 as it no longer needs to mix the signals.

Alternatively the two voice signals could be mixed in the audio codec 9and delivered over only one AC channel on the AC link. Whilst this mayreduce audio quality slightly, it does free up one of the AC channelsfor other applications. This also reduces some processing load of theapplication processor 4 as the mix of the signals is done in the codec9. Also the separated streams (Near End separated from the Far End)enable additional enhancement processing for each stream by itself ifdesired (e.g. remove Far End signal from Near End one to provide echoremoval, noise suppression on Near End for digital dictationapplications; enhanced streams before compression and storing inmemory).

Also the use of two AC channels on the AC-link 7 to deliver voice to theapplications processor 4 further allows additional functionality as theunmixed audio or voice channels can be used separately by theapplications processor. For example whilst recording the voice call(both near and far end), the near end voice (from the wireless headset12) may separately be used for voice activated functions such as voiceactivation menu or voice memo pad.

This is described in more detail with reference to FIG. 12 c. The nearend signal (path 53) is routed directly using one slot of the AC link 7(path 53 a), and is also mixed (path 53 b) with the far-end signal (path54), in digital or analogue domain, and sent across another slot on theAC-link (path 55). Again a wide range of analogue or digital sample rateconversion modes are available according to the choice of internalconfiguration of the audio codec.

Note that the features just described in FIGS. 12 b and 12 c can beachieved both with and without the pass devices 37 a and 37 b, so that areduced audio application set (including the applications of FIGS. 3 b,3 c, and 10 c for example but not for example those of FIGS. 4 b, 10 b,11 b, 11 c, 11 d, 11 e) may be implemented on non-dual mode audio busarchitectures. However it is apparent that the dual mode audio busallows many extra functions at little expense.

FIG. 13 a shows connections on the PCM bus in the case of a duplex bus36 where the audio codec 9 has a dual PCM interface 9 a to a dual modePCM bus, i.e. 4 data wires in total, two for each part of the bus, andwhere there is no PCM link from the applications processor 4 to the PCMbus 36. This is similar to the architecture of FIG. 10 a, but using twoor duplex data buses instead of just one.

FIG. 13 b shows the signal flow for the application similar to thatdiscussed in relation to FIG. 11 b. Signal flow is very similar, exceptthat the output 25 from the audio codec to the wireless headset nowpasses directly from the audio codec 9 across the PCM bus (36 ax) ratherthan via the AC-link 7 and the applications processor 4.

FIG. 13 c shows the signal flow for the application similar to thatdiscussed in relation to FIG. 11 b. Signal flow is very similar, exceptthat the output 26 d from the audio codec to the wireless headset 12 nowpasses directly from the audio codec 9 across the PCM bus 36 bx ratherthan via the AC-link 7 and the applications processor 4. Similarly thesignal flow 26 c from the wireless headset 12 passes directly to theaudio codec 9 across the PCM bus 36 ax. Thus three signal flows passbetween the audio codec 9 and the applications processor 4, howeverthese can all be accommodated on the single AC bus, which as describedpreviously includes multiple channel capability using time dividedslots. Three such slots or AC channels are used in this application, oneof each mapped respectively to an incoming and outgoing PCM channel onone of the PCM interfaces, and to an incoming channel on the other PCMinterface.

FIG. 13 d shows the signal flow for the application similar to thatdiscussed in relation to FIG. 11 d. Signal flow is very similar, exceptthat the output 26 d from the audio codec to the wireless headset nowpasses directly from the audio codec across the PCM bus rather than viathe AC-link and the applications processor; and the signal flow 26 cfrom the wireless codec 11 to the audio codec 9 passes directly throughthe PCM bus 36 ax to the audio codec rather than through theapplications processor 4.

FIG. 13 e shows the signal flow for the application similar to thatdiscussed in relation to FIG. 11 e. Signal flow is very similar, exceptthat the output 25 from the audio codec to the wireless headset nowpasses directly from the audio codec across the PCM bus rather than viathe AC-link and the applications processor.

The skilled person will recognise that the above-described apparatus andmethods may be embodied as processor control code, for example on acarrier medium such as a disk, CD- or DVD-ROM, programmed memory such asread only memory (Firmware), or on a data carrier such as an optical orelectrical signal carrier. For many applications embodiments of theinvention will be implemented on a DSP (Digital Signal Processor), ASIC(Application Specific Integrated Circuit) or FPGA (Field ProgrammableGate Array). Thus the code may comprise conventional programme code ormicrocode or, for example code for setting up or controlling an ASIC orFPGA. The code may also comprise code for dynamically configuringre-configurable apparatus such as re-programmable logic gate arrays.Similarly the code may comprise code for a hardware description languagesuch as Verilog™ or VHDL (Very high speed integrated circuit HardwareDescription Language) and their analogue extensions. As the skilledperson will appreciate, the code may be distributed between a pluralityof coupled components in communication with one another. Whereappropriate, the embodiments may also be implemented using code runningon a field-(re)programmable analogue array or similar device in order toconfigure analogue hardware.

The skilled person will also appreciate that the various embodiments andspecific features described with respect to them could be freelycombined with the other embodiments or their specifically describedfeatures in general accordance with the above teaching. The skilledperson will also recognise that various alterations and modificationscan be made to specific examples described without departing from thescope of the appended claims.

1. A digital audio device comprising: an applications processor; acommunications processor; and a wireless codec; the device having a modeof operation in which: the applications processor is arranged to receivea first digital audio signal and the wireless codec is arranged totransmit the first digital audio signal wirelessly to a peripheraldevice; and the applications processor is arranged to respond to thereception of a wireless telephony call at the device by receiving apreviously-recorded second digital audio signal and the communicationsprocessor is arranged to transmit the second digital audio signal insaid wireless telephony call simultaneously with the transmission of thefirst digital audio signal by the wireless codec.
 2. A digital audiodevice according to claim 1 which further comprises a memory and inwhich the applications processor is arranged to receive the firstdigital audio signal from the memory.
 3. A digital audio deviceaccording to claim 2 in which the first audio signal is a music signal.4. A digital audio device according to claim 1 which further comprises amemory and in which the application processor is arranged to receive thesecond digital audio signal from the memory.
 5. A digital audio deviceaccording to claim 1 in which the wireless codec is arranged to receivea third digital audio signal wirelessly from said peripheral devicesimultaneously with the transmission of the first digital audio signalby the wireless codec and the transmission of the second digital audiosignal by the communications processor, and the applications processoris arranged to store the third digital audio signal.
 6. A digital audiodevice according to claim 5 which further comprises a memory and inwhich the applications processor is arranged to store the third digitalaudio signal in the memory.
 7. A method of operating a wirelesstelephony device, the method comprising: wirelessly transmitting a firstdigital audio signal to a peripheral device; and responding to thereception of a wireless telephony call by transmitting apreviously-recorded second digital audio signal in the wirelesstelephony call simultaneously with the transmission of the first digitalaudio signal to the peripheral device.
 8. A method according to claim 7in which the first digital audio signal is retrieved from a memory.
 9. Amethod according to claim 8 in which the first audio signal is a musicsignal.
 10. A method according to claim 7 in which the second digitalaudio signal is retrieved from a memory.
 11. A method according to claim7 further comprising wirelessly receiving a third digital audio signalfrom said peripheral device simultaneously with the transmission of thefirst digital audio signal to the peripheral device and the transmissionof the second digital audio signal in the wireless telephony call, andstoring the third digital audio signal.
 12. A digital audio devicecomprising: an applications processor; a communications processor; and awireless codec; the device having a mode of operation in which: theapplications processor is arranged to receive a first digital audiosignal, and the wireless codec is arranged to transmit the first digitalaudio signal wirelessly to a peripheral device; and the communicationsprocessor is arranged to receive a second digital audio signal in adigital telephony call simultaneously with the transmission of the firstdigital audio signal by the wireless codec, and the applicationsprocessor is arranged to store the second digital audio signal.
 13. Adigital audio device according to claim 12 which further comprises amemory and in which the applications processor is arranged to receivethe first digital audio signal from the memory.
 14. A digital audiodevice according to claim 13 in which the first audio signal is a musicsignal.
 15. A digital audio device according to claim 12 which furthercomprises a memory and in which the applications processor is arrangedto store the second digital audio signal in the memory.
 16. A digitalaudio device according to claim 12 in which the applications processoris arranged to mix the second digital audio signal with the firstdigital audio signal, and the wireless codec is arranged to transmit thefirst digital audio signal wirelessly to said peripheral device bytransmitting it mixed with the second digital signal.
 17. A digitalaudio device according to claim 16 wherein a user is enabled to acceptthe digital telephony call, or to allow the second digital audio signalto continue to be stored by the applications processor without answeringthe digital telephony call, in response to the transmission to saidperipheral device of the first digital audio signal mixed with thesecond digital audio signal.
 18. A digital audio device according toclaim 12 in which the wireless codec is arranged to receive a thirddigital audio signal wirelessly from said peripheral devicesimultaneously with the transmission of the first digital audio signalby the wireless codec and the reception of the second digital audiosignal by the communications processor, and the applications processoris arranged to store the third digital audio signal.
 19. A digital audiodevice according to claim 18 which further comprises a memory and inwhich the applications processor is arranged to store the third digitalaudio signal in the memory.
 20. A method of operating a wirelesstelephony device, the method comprising: wirelessly transmitting a firstdigital audio signal to a peripheral device; and receiving a seconddigital audio signal in a wireless telephony call simultaneously withthe transmission of the first digital audio signal to the peripheraldevice, and storing said second digital audio signal.
 21. A methodaccording to claim 20 in which the first digital audio signal isretrieved from a memory.
 22. A method according to claim 21 in which thefirst audio signal is a music signal.
 23. A method according to claim 20in which the second digital audio signal is mixed with the first digitalaudio signal, and the step of wirelessly transmitting the first digitalaudio signal comprises transmitting it mixed with the second digitalsignal.
 24. A method according to claim 23 wherein a user is enabled toaccept the digital telephony call, or to allow the second digital audiosignal to continue to be stored without answering the digital telephonycall, in response to the transmission to the peripheral device of thefirst digital audio signal mixed with the second digital audio signal.25. A method according to claim 20 further comprising wirelesslyreceiving a third digital audio signal from said peripheral devicesimultaneously with the transmission of the first digital audio signalto the peripheral device and the reception of the second digital audiosignal in the wireless telephony call, and storing the third digitalaudio signal.
 26. A digital audio device comprising: an applicationsprocessor; a communications processor; and a wireless codec; the devicehaving a mode of operation in which: the applications processor isarranged to receive a first digital audio signal and the wireless codecis arranged to transmit the first digital audio signal wirelessly to aperipheral device; the applications processor is arranged to respond tothe reception of a wireless telephony call at the device by receiving apreviously-recorded second digital audio signal and the communicationsprocessor is arranged to transmit the second digital audio signal insaid wireless telephony call simultaneously with the transmission of thefirst digital audio signal by the wireless codec; and the communicationsprocessor is arranged to receive a third digital audio signal in saiddigital telephony call subsequently to the transmission of the seconddigital audio signal in said wireless telephony call and simultaneouslywith the transmission of the first digital audio signal by the wirelesscodec, and the applications processor is arranged to store the thirddigital audio signal.
 27. A digital audio device according to claim 26which further comprises a memory and in which the applications processoris arranged to receive the first digital audio signal from the memory.28. A digital audio device according to claim 27 in which the firstaudio signal is a music signal.
 29. A digital audio device according toclaim 26 which further comprises a memory and in which the applicationprocessor is arranged to receive the second digital audio signal fromthe memory.
 30. A digital audio device according to claim 26 whichfurther comprises a memory and in which the applications processor isarranged to store the third digital audio signal in the memory.
 31. Adigital audio device according to claim 26 in which the applicationsprocessor is arranged to mix the third digital audio signal with thefirst digital audio signal, and the wireless codec is arranged totransmit the first digital audio signal wirelessly to said peripheraldevice, simultaneously with the reception of the third digital audiosignal by the communications processor, by transmitting the firstdigital audio signal mixed with the third digital signal.
 32. A digitalaudio device according to claim 31 wherein a user is enabled to acceptthe digital telephony call, or to allow the third digital audio signalto continue to be stored by the applications processor without answeringthe digital telephony call, in response to the transmission to saidperipheral device of the first digital audio signal mixed with the thirddigital audio signal.
 33. A digital audio device according to claim 26in which the wireless codec is arranged to receive a fourth digitalaudio signal wirelessly from said peripheral device simultaneously withthe transmission of the first digital audio signal by the wirelesscodec, and the applications processor is arranged to store the fourthdigital audio signal.
 34. A digital audio device according to claim 33which further comprises a memory and in which the applications processoris arranged to store the fourth digital audio signal in the memory. 35.A method of operating a wireless telephony device, the methodcomprising: wirelessly transmitting a first digital audio signal to aperipheral device; responding to the reception of a wireless telephonycall by transmitting a previously-recorded second digital audio signalin the wireless telephony call simultaneously with the transmission ofthe first digital audio signal to the peripheral device; and receiving athird digital audio signal in a wireless telephony call subsequently tothe transmission of the second digital audio signal in the wirelesstelephony call and simultaneously with the transmission of the firstdigital audio signal to the peripheral device, and storing said thirddigital audio signal.
 36. A method according to claim 35 in which thefirst digital audio signal is retrieved from a memory.
 37. A methodaccording to claim 36 in which the first audio signal is a music signal.38. A method according to claim 35 in which the second digital audiosignal is retrieved from a memory.
 39. A method according to claim 35 inwhich the third digital audio signal is mixed with the first digitalaudio signal, and the step of wirelessly transmitting the first digitalaudio signal, simultaneously with the reception of the third digitalaudio signal in the wireless telephony call, comprises transmitting thefirst digital audio signal mixed with the third digital signal.
 40. Amethod according to claim 39 wherein a user is enabled to accept thedigital telephony call, or to allow the third digital audio signal tocontinue to be stored without answering the digital telephony call, inresponse to the transmission to the peripheral device of the firstdigital audio signal mixed with the third digital audio signal.
 41. Amethod according to claim 35 further comprising wirelessly receiving afourth digital audio signal from said peripheral device simultaneouslywith the transmission of the first digital audio signal to theperipheral device, and storing the fourth digital audio signal.
 42. Adigital audio device comprising: an applications processor; and awireless codec; the device having a mode of operation in which: theapplications processor is arranged to receive a first digital audiosignal and the wireless codec is arranged to transmit the first digitalaudio signal wirelessly to a peripheral device; and the wireless codecis arranged to receive a second digital audio signal wirelessly fromsaid peripheral device simultaneously with the transmission of the firstdigital audio signal by the wireless, and the applications processor isarranged to store the second digital audio signal.
 43. A digital audiodevice according to claim 42 which further comprises a memory and inwhich the applications processor is arranged to receive the firstdigital audio signal from the memory.
 44. A digital audio deviceaccording to claim 43 in which the first audio signal is a music signal.45. A digital audio device according to claim 42 which further comprisesa memory and in which the applications processor is arranged to storethe second digital audio signal in the memory.
 46. A method of operatinga wireless telephony device, the method comprising: wirelesslytransmitting a first digital audio signal to a peripheral device; andwirelessly receiving a second digital audio signal from said peripheraldevice simultaneously with the transmission of the first digital audiosignal to the peripheral device, and storing the second digital audiosignal.
 47. A method according to claim 46 in which the first digitalaudio signal is retrieved from a memory.
 48. A method according to claim47 in which the first audio signal is a music signal.
 49. A wirelesstelephony device comprising a digital audio device according to claim 1.50. A wireless telephony device comprising a digital audio deviceaccording to claim
 12. 51. A wireless telephony device comprising adigital audio device according to claim
 26. 52. A wireless telephonydevice comprising a digital audio device according to claim
 42. 53. Aportable cellular wireless telephony device comprising a digital audiodevice according to claim
 1. 54. A portable cellular wireless telephonydevice comprising a digital audio device according to claim
 12. 55. Aportable cellular wireless telephony device comprising a digital audiodevice according to claim
 26. 56. A portable cellular wireless telephonydevice comprising a digital audio device according to claim
 42. 57. Alaptop computer with telephony capability comprising a digital audiodevice according to claim
 1. 58. A laptop computer with telephonycapability comprising a digital audio device according to claim
 12. 59.A laptop computer with telephony capability comprising a digital audiodevice according to claim
 26. 60. A laptop computer with telephonycapability comprising a digital audio device according to claim
 42. 61.A mobile phone comprising a digital audio device according to claim 1.62. A mobile phone comprising a digital audio device according to claim12.
 63. A mobile phone comprising a digital audio device according toclaim
 26. 64. A mobile phone comprising a digital audio device accordingto claim 42.